Emulation systems typically emulate circuit designs using one or more reconfigurable logic units. For example, an emulation system may have one or more field-programmable gate arrays (FPGAs) and/or processors that emulate the design. Each FPGA may include a plurality of reconfigurable logic elements. The reconfigurable logic units (e.g., FPGA chips, processors, and/or reconfigurable logic elements) may produce internal states and external outputs during running of the emulation.
During emulation, it is often desirable to be able to take some action as a result of a particular emulation event occurring. For example, a particular combination of internal states of reconfigurable logic elements may be an emulation event that is of interest. If the emulator achieves the emulation event of interest, then the emulator may be configured to take a specified action. This is called triggering.
Triggering can be based on a specified set or subset of the total internal states and/or external outputs. To provide for triggering capability based on internal states, the emulation system needs to have visibility into the internal states. In large emulation systems, there are Y*X reconfigurable logic elements (where Y is the number of reconfigurable logic chips and X is the number of reconfigurable logic elements per chip). Typically, to implement triggering, the internal states of a subset N of the reconfigurable logic elements are collected during emulation runtime. These are called trace bits. However, N is often several orders of magnitude larger than the total number of bits T that are actually part of and relevant to a trigger. Thus, T<<N. This is usually true not only at the system level, but also at the chip level. Because the remaining trace bits N−T that are collected are irrelevant to the outcome of the trigger, N−T of the N trace bits are also irrelevant to triggering.
To determine whether a trigger condition has occurred, the N trace bits are compared against pre-stored compare bits. If the comparison results in a match, then the trigger condition has occurred. However, such a comparison needs to take into account the fact that N−T of the trace bits (and N−T of the compare bits) do not affect the outcome of the comparison. Thus, a set of N “don't care” bits are also stored, each one indicating whether a related stored compare bit affects the outcome of the comparison. In other words, 2N bits (N compare bits and N don't care bits) are stored. These 2N bits are stored in memory such as a static random access memory (SRAM).
An SRAM-based trigger system uses mainly read power. Write power is mostly involved only at system initialization. In the above-described system, two bits are read out of the SRAM for each trace bit that is potentially part of the trigger. SRAMs are characterized by the amount of power required to read a single bit, plus miscellaneous power. For T useful compare bits, the useful power Puseful is proportional to 2T. However, since 2N bits are actually read, the total power used by such a trigger system is proportional to 2N>>2T, and the total wasted/useless power Pwaste is proportional to 2(N−T)>>2T. Thus, Pwaste is proportional to ((N−T)/T)*Puseful, and Puseful<<Pwaste. Clearly, significant read power is wasted in such a triggering mechanism. This wasted power is multiplied many-fold when (as is often the case) trigger comparison is performed often, such as at least every clock cycle.